The present invention relates to a method of measuring a resistivity of a sidewall of a contact hole during a semiconductor manufacturing process. More specifically, the present invention relates to a method of measuring a resistivity of an organic film attached to a sidewall of a contact hole.
Conventionally, there has been an etching method for forming a fine contact hole, in which a dry etching is performed on an object to be processed (for example, a semiconductor wafer or a wafer) (refer to Patent References 1 and 2). As a size of a semiconductor device decreases, an aspect ratio of a contact hole (a ratio of an inner diameter or a width of a contact hole to a depth or a height thereof) increases. Accordingly, there have been several problems associated with the decrease in the size such as an etching stop or an abnormal shape of a contact hole during an etching process, the μ loading effect (a phenomenon in which an etching speed varies due to a variance in a density of a chip pattern on a wafer), and the likes. In particular, charge-up damage due to an electron shading effect may cause a serious problem.
Patent Reference 1: Japanese Patent Publication NO. 2000-200771
Patent Reference 2: Japanese Patent Publication NO. 2001-053057
FIG. 10 is a schematic sectional view showing a wafer for explaining the electron shading effect. As shown in FIG. 10, an MOS transistor is formed on a semiconductor substrate 1 as a part of the wafer. The MOS transistor includes a source region 1a and a drain region 1b formed of an impurity diffused layer arranged on the semiconductor substrate 1 with a specific interval in between. Further, the MOS transistor includes a gate insulating film 2 formed of a silicon dioxide (a SiO2 film) and disposed on the source region 1a and the drain region 1b, and a gate electrode 3 formed on the gate insulating film 2.
In the MOS transistor, an interlayer insulating film 4 formed of a SiO2 film covers an entire surface including the gate electrode 3. A resist pattern 5 formed of a photo-resist film is formed on the interlayer insulating film 4. A dry etching is performed using plasma with the resist pattern 5 as a mask for forming a contact hole 6 in the interlayer insulating film 4.
In the dry etching, electrons 7 and positive ions 8 are generated with plasma. When the contact hole 6 is etched and an aspect ratio thereof increases, the electrons 7 collide with a sidewall of the resist pattern 5. On the other hand, the positive ions 8 tend to vertically irradiate on a bottom portion of the contact hole 6. Accordingly, the sidewall of the resist pattern and an upper inner wall of the contact hole charged up with negative charges.
In this case, the negative charges form an electric field functioning as a barrier against the electrons 7. Accordingly, when the electrons 7 have a small velocity component in a vertical direction relative to the bottom portion of the contact hole 6, the electrons 7 are decelerated with the electric field or even bounced back, thereby making it difficult for the electrons 7 to enter the resist pattern 5. The phenomenon is called the electron shading effect.
When the electron shading effect occurs, a large number of the positive ions 8 irradiate on the bottom portion of the contact hole 6 as compared with that of the electrons 7. Accordingly, a lower sidewall portion of the contact hole 6 (for example, a sidewall of the gate electrode 3 as a lower layer wiring portion) is charged up with positive charges. In forming the contact hole 6, when a charged up potential is generated in the gate electrode 3 as the lower layer wiring portion, there may be serious charge up damage such as damage in the gate insulating film 2 formed below the gate electrode 3.
In order to suppress or prevent the charge up damage, Patent Reference 1 has disclosed a technology. In the technology disclosed in Patent Reference 1, a plasma processing method is adopted for preventing the charge up damage due to the electron shading effect, so that it is possible to form a contact hole with a desirable high aspect ratio. Patent Reference 2 has disclosed a method of wiring and producing an MOS transistor capable of suppressing the charge up damage.
Non-Patent References 1 and 2 have disclosed that when a contact hole is formed through a plasma etching with a resist pattern formed of a resist film as a mask, a fluorocarbon (CF) gas is used as an etching gas. As a result, an organic film with conductivity is deposited on a bottom surface and a sidewall of the contact hole, thereby alleviating charge up generated in a lower layer wiring portion.
Non-Patent Reference 1: J. Vac. Technol. B. 22[2] (March/April 2004) T. Shimura P. 533-538
Non-Patent Reference 2: Proc. Symp. on Dry Process (2002) S. Soda P. 281-284
In Non-Patent References 1 and 2, the organic film deposited on the bottom surface and the sidewall of the contact hole is eventually removed when the resist film is removed. It is necessary to form the organic film having a sufficient amount, otherwise it is difficult to reduce the electron shading effect. In order words, in order to reduce the electron shading effect and improve reliability of the semiconductor manufacturing process, it is necessary to stably form the organic film having a sufficient amount in the semiconductor manufacturing process. To this end, it is imperative to measure conductivity (that is, a resistivity) of the organic film deposited on the bottom surface and the sidewall of the contact hole.
As described above, in forming the contact hole, it is necessary to form the organic film having a sufficient amount on the sidewall of the contact hole. To this end, it is imperative to measure a resistivity of the organic film.
According to Non-Patent Reference 1, the resistivity of the organic film is measured using a method shown in FIG. 11. FIG. 11 is a schematic view showing a conventional method of measuring the resistivity of the organic film deposited on the sidewall of the contact hole.
As shown in FIG. 11, in the conventional method of measuring the resistivity of the organic film, first, a mock-up model (a sample) having a contact hole is prepared. In the sample, a lower electrode 12 formed of a poly-silicon film is formed on a silicon (Si) substrate 10 with a SiO2 film 11 as an insulating film in between. An upper electrode 14 formed of a poly-silicon film is formed on the lower electrode 12 with a SiO2 film 13 in between, and a SiO2 film 15 is formed on the upper electrode 14. A contact hole 16 is formed in the SiO2 film 15, the upper electrode 14, and the SiO2 film 13 through a plasma etching with a resist pattern (not shown) as a mask. The resist pattern is removed after the contact hole 16 is formed.
In the next step, the sample is placed in an etching chamber. In the etching chamber, an organic film is deposited on a sidewall of the contact hole 16 using a fluorocarbon gas (C4F8). Then, argon ions (Ar) are irradiated on the sample for promoting polymerization of the organic film on the sidewall of the contact hole 16. In the last step, after the sample is removed from the etching chamber, a voltage is applied between the upper electrode 14 and the lower electrode 12, thereby measuring a current value to determine the resistivity of the organic film.
In the conventional method of measuring the resistivity of the organic film, the organic film is deposited after the contact hole 16 is formed in the sample. Accordingly, the organic film does not contain a sputter compound of the resist pattern or an etching reaction product.
In an ordinary dry etching process, an organic film is deposited concurrently with the Ar irradiation. In the conventional method of measuring the resistivity of the organic film, on the other hand, the Ar irradiation is performed after the organic film is deposited. Accordingly, the organic film has a property different from that of an organic film deposited on a sidewall of a contact hole formed through an ordinary oxide film contact etching (that is, the organic film formed in the ordinary semiconductor manufacturing process). Accordingly, it is difficult to form an actual organic film formed in the ordinary semiconductor manufacturing process.
To this end, in the method shown in FIG. 11, after the contact hole 16 is formed, it may be arranged to measure the resistivity of the organic film deposited on the sidewall of the contact hole using the sample without removing the resist pattern through asking or cleaning. In this case, the resist film and the organic film are deposited on the lower electrode 12 and the upper electrode 14. Accordingly, it is difficult to secure a sufficient electrical contact for applying a voltage to measure a current value, thereby making it difficult to measure the resistivity of the organic film.
Alternatively, an additional step may be provided for exposing a part of the lower electrode 12 and the upper electrode 14 where an electrical contact is established. However, in this case, it is necessary to dispose an extra resist pattern for exposing the part of the lower electrode 12 and the upper electrode 14 through etching. Accordingly, an original organic film may have a varied property, thereby making it difficult to measure the resistivity of the organic film.
In view of the problem described above, an object of the present invention is to provide a method of measuring a resistivity of a sidewall of a contact hole during a semiconductor manufacturing process, in which it is possible to accurately measure the resistivity of the organic film.
Further objects and advantages of the invention will be apparent from the following description of the invention.